Using Timers in the MAXQ Famil

文章摘要：The following code should be called whenever the pulse is to be triggered. TriggerPulse:move T2CNA2.1, #1 ; set the single shot bit to start the timerretThe following is a piece of the interrupt code.IntHandler:move c, T2CNB2.3jump nc, NonTimerIntmove T2CNB2.3, #0 ; turn off overflow bit so interrup

Using Timers in the MAXQ Famil,标签：计算机控制技术,工厂电气控制技术,http://www.88dzw.com

The following code should be called whenever the pulse is to be triggered.

TriggerPulse:
	move T2CNA2.1, #1 ; set the single shot bit to start the timer
ret
The following is a piece of the interrupt code.
IntHandler:
move c, T2CNB2.3
jump nc, NonTimerInt
move T2CNB2.3, #0 ; turn off overflow bit so interrupt is serviced
; code for end of pulse here...

NonTimerInt:
	; other interrupt code here.

reti

Compare Example 3 - Timed interrupts
The following code will generate two interrupts, one every 125 microseconds and a second one every millisecond. It uses one timer split into two eight-bit timers. Since both eight-bit timers will be running from the same input clock, we want to pick a clock divisor that will allow both timers to have a count of less than 256 (the maximum for a eight-bit counter). Using the alternate clock as source provides us with a way to get both timings without needing to divide down the system clock, at the cost of some accuracy: the actual timing is closer to 122 microseconds for the high counter and 0.98 milliseconds for the low counter since the alternate clock runs at 32768 Hz and no even divisor for the required periods is available. We will get 1024 interrupts per second from the low counter and 8192 interrupts per second from the high counter. Both high and low interrupts are enabled and the type of interrupt is identified by the TF2 and TF2L bits which must be cleared to service the interrupt.

; This code sets up the timer and should be run once
	; set up Int handler
	move    IV, #IntHandler	    ; Set interrupt vector.
    	move    IC.0, #1            ; Enable global interrupts.
    	move    IMR.3, #1           ; Enable interrupts for module 3.
	; timer 0 is in module 3

	move 	T2CFG0, #088h ;
; 1000,1000 -- use 32 kHz clock (1), divide by 1 (000),
;	8 bit mode (1), compare mode (00), c/t2=timer (0)

	move 	T2CNB0, #080h
; 1000,0000 -- ET2L on, low interrupt will be generated (1), secondary OE off (0),
;	T2POL1 = not used (0), reserved(0)
;	TF2 is generated by the timer (0), TF2L is generated by timer (0),
;   	TCC2 is not used (0), TC2L is not used (0)

	move 	T2CNA0, #080h
; 1000,0000 -- ET2 on, interrupt will be generated (1), primary OE off (0),
;	T2POL0 is not needed (0), TR2L off, will be set later (0)
;	TR2 off, will be set later (0), CPRL2 is not needed (0),
;   	SS2 is not needed (0), gating disabled (0)

	move	T2H0, #0FCh ; set to reload value to keep first pulse from being extra long
	move 	T2RH0, #0FCh ; reload value (0x100 - 0xFC = 4 ticks)
	move 	T2CH0, #000h ;

	move	T2V0, #0E0h ; set to reload value to keep first pulse from being extra long
	move 	T2R0, #0E0h ; reload value (0x100 - 0xE0 = 32 ticks)
	move 	T2C0, #000h ;

	move	ACC, T2CNA0 ; turn on high run and low run (TR2, TR2L)
	or	#018h ;
	move	T2CNA0, ACC

The following is part of the interrupt handler code:

IntHandler:
	move c, T2CNB0.3
	jump nc, No8KHz
	; code for 8KHz interrupt here
	move T2CNB0.3, #0


No8KHz:
	move c, T2CNB0.2
	jump nc, No1KHz
	; code for 1KHz interrupt here
	move T2CNB0.2, #0


No1KHz:
	; other interrupt code here

reti

Capture Example - Time an incoming waveform
This example times an incoming signal. This code uses the second timer (they are numbered 0,1, and 2) and is set up to time the duration of a high pulse. It does not start timing until a rising edge is seen. The CPRL2 bit enables a reload upon capture so that subsequent pulses can also be timed. The T2POL [0] and SS2 bits have slightly different meanings in this mode. The SS2 bit (single shot) is used to inhibit counting until the beginning edge is detected. This enables the timer to be set up at any time, even when the input is currently high since the timer will not start until the next rising edge. The T2POL [0] bit selects the gating level instead of the output polarity as in the previous examples. A gating level of 0 prevents the counter from running while the input is low. This example is geared for longer pulses and divides the system clock by 128. With a system clock frequency of 4.9152 MHz, the timer has a resolution of approximately 26 microseconds, and can count to 1.7 seconds before overflowing.

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