Using Timers in the MAXQ Famil

文章摘要：T2CNA contains gating enable, single shot, reload enable, run enable, low run enable, primary output polarity, primary output enable, and interrupt enable bits. The gating enable bit (G2EN) allows the counter to be selectively disabled. The single shot bit (SS2) allows the timer to run until the ne

Using Timers in the MAXQ Famil,标签：计算机控制技术,工厂电气控制技术,http://www.88dzw.com
T2CNA contains gating enable, single shot, reload enable, run enable, low run enable, primary output polarity, primary output enable, and interrupt enable bits.

The gating enable bit (G2EN) allows the counter to be selectively disabled. The single shot bit (SS2) allows the timer to run until the next overflow condition, at which point the timer halts.

The capture and reload bit (CPRL2) instructs the timer to capture its value into its capture register and reload the value from the reload register on an external edge. CPRL2 is not used in the compare and counter modes.

The run enable bit (TR2) allows the primary counter to run and the low run enable bit (TR2L) allows the secondary counter to run when in eight-bit mode.

The primary polarity select bit (T2POL0) selects the initial polarity of the primary output. Changing this bit after the output has been enabled via T2OE0 has no effect. Setting the primary output enable bit (T2OE0) turns on the output for the primary pin and sets its value equal to the value in the polarity bit (T2POL0).

Setting the primary interrupt enable (ET2) allows interrupts to be generated provided that they are enabled for the timer's module (set the appropriate bit in the IMR register) and global interrupts have been enabled (IC register bit 0 set to 1). Interrupts are generated when the primary counter overflows (reaches FFFFh) or matches the compare register. In these cases the appropriate bit (TF2 for overflow or TCC2 for a compare) will be set and should be reset by firmware in the interrupt handler. Failing to reset these bits will cause repeated interrupts until they are reset or the interrupt has been disabled.

T2CNB contains compare and overflow flags, the secondary interrupt enable, and the secondary output polarity and enable bits.

The capture/compare flag (TCC2) is set when the primary counter value matches the compare value.

The low capture/compare flag (TC2L) is similar to TCC2, but is set only when in eight-bit mode and the low or secondary counter matches the low compare value.

The overflow flag (TF2) is set when the primary counter overflows. The low overflow flag (TF2L) is similar to TF2, but is set only when in eight-bit mode and the low or secondary counter overflows. The secondary polarity select bit (T2POL1) selects the initial polarity of the secondary or B output pin. Changing this bit after the output has been enabled via T2OE1 has no effect. Setting the secondary output enable bit (T2OE1) turns on the output for the secondary pin and sets its value equal to the value in the polarity bit (T2POL1). The secondary output is not directly linked to the secondary counter, since in sixteen-bit mode the primary counter sources it but in eight-bit mode the low counter sources it.

Setting the secondary interrupt enable (ET2L) allows interrupts to be generated when the TF2L or TC2L bits are set by an overflow (TF2L) or compare (TC2L) of the secondary or low eight-bit counter when in eight-bit mode. The ET2L bit is not used in sixteen-bit mode.

上一页  [1] [2] [3] [4] [5] [6] [7] [8]  下一页