VHDL设计的串口通信程序

文章摘要： PROCESS(clk,rst) BEGIN IF (NOT rst = ’1’) THEN cnt_delay <= "00000000000000000000"; start_delaycnt <= ’0’; ELSIF(clk’EVENT AND clk=’1’)THEN IF (start_delaycnt = ’1’) THEN IF (cnt_delay /= "11000011010100000000"

VHDL设计的串口通信程序,标签：eda技术,eda技术实用教程,http://www.88dzw.com

   PROCESS(clk,rst)
   BEGIN
      
      IF (NOT rst = ’1’) THEN
         cnt_delay <= "00000000000000000000";   
         start_delaycnt <= ’0’;   
      ELSIF(clk’EVENT AND clk=’1’)THEN
         IF (start_delaycnt = ’1’) THEN
            IF (cnt_delay /= "11000011010100000000") THEN
               cnt_delay <= cnt_delay + "00000000000000000001";   
            ELSE
               cnt_delay <= "00000000000000000000";   
               start_delaycnt <= ’0’;   
            END IF;
         ELSE
            IF ((NOT key_input=’1’) AND (cnt_delay = "00000000000000000000")) THEN
               start_delaycnt <= ’1’;   
            END IF;
         END IF;
      END IF;
   END PROCESS;

   PROCESS(clk,rst)
   BEGIN
      
      IF (NOT rst = ’1’) THEN
         key_entry1 <= ’0’;   
      ELSIF(clk’EVENT AND clk=’1’)THEN
         IF (key_entry2 = ’1’) THEN
            key_entry1 <= ’0’;   
         ELSE
            IF (cnt_delay = "11000011010100000000") THEN
               IF (NOT key_input = ’1’) THEN
                  key_entry1 <= ’1’;   
               END IF;
            END IF;
         END IF;
      END IF;
   END PROCESS;

   PROCESS(clk,rst)
   BEGIN
      
      IF (NOT rst = ’1’) THEN
         div_reg <= "0000000000000000";   
      ELSIF(clk’EVENT AND clk=’1’)THEN

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