实现MAXQ2000微控制器的JTAG加载主机
[09-13 17:04:13] 来源:http://www.88dzw.com 控制技术 阅读:8661次
文章摘要:从机评估板还在插座J3上安装了LCD子卡(MAXQ2000-K01)。表2列出了两块电路板(以及串口至JTAG电路板)的跳线和DIP开关设置。注意:应断开未列出的所有跳线。图1所示为最终设置。表2. 电路板开关和跳线设置 BoardSwitch or JumperSettingNotesSerial-to-JTAG BoardJH1Connected JH2ConnectedJH3ConnectedSupplies 5V power over JTAG cableMaster MAXQ2000 EV KitJU1Pins 1 and 2 connectedPowers VDD from 2.5
实现MAXQ2000微控制器的JTAG加载主机,标签:计算机控制技术,工厂电气控制技术,http://www.88dzw.com从机评估板还在插座J3上安装了LCD子卡(MAXQ2000-K01)。表2列出了两块电路板(以及串口至JTAG电路板)的跳线和DIP开关设置。注意:应断开未列出的所有跳线。图1所示为最终设置。
表2. 电路板开关和跳线设置
Board | Switch or Jumper | Setting | Notes |
Serial-to-JTAG Board | JH1 | Connected | |
JH2 | Connected | ||
JH3 | Connected | Supplies 5V power over JTAG cable | |
Master MAXQ2000 EV Kit | JU1 | Pins 1 and 2 connected | Powers VDD from 2.5V supply |
JU2 | Pins 1 and 2 connected | Powers VDDIO from 3.6V supply | |
JU3 | Pins 1 and 2 connected | Powers VLCD from 3.6V supply | |
JU11 | Connected | Powers kit board from JTAG 5V supply | |
DIP SW1 | Switches #4 and #8 ON; all other switches OFF | Enables serial port 0 output to J5 | |
DIP SW3 | All switches OFF | ||
DIP SW6 | All switches OFF | ||
Slave MAXQ2000 EV Kit | JU1 | Pins 1 and 2 connected | Powers VDD from 2.5V supply |
JU2 | Pins 1 and 2 connected | Powers VDDIO from 3.6V supply | |
JU3 | Pins 1 and 2 connected | Powers VLCD from 3.6V supply | |
DIP SW1 | All switches OFF | ||
DIP SW3 | All switches OFF | ||
DIP SW6 | All switches OFF |

图1. JTAG演示板配置
MAXQ JTAG接口
MAXQ微控制器的JTAG接口由四条信号线组成,用于测试访问端口(TAP)控制器的信息输入和输出。TAP控制器支持对MAXQ启动加载程序的访问,提供在线调试功能(注意,调试主机的实现和启动加载程序主机的实现类似,但是已经超出了本应用笔记的范围)。表3对四条JTAG信号线进行了说明。表3. JTAG接口信号
JTAG Signal | Signal Name | Direction (Master) | Direction (Slave) | Signal Description |
TMS | Test Mode Select | Output | Input | This signal line, along with the TCK line, is used to shift the TAP controller from one operational state to the next. |
TCK | Test Clock | Output | Input | This signal provides the clock for the JTAG interface. The JTAG clock is limited to a maximum of the slave's clock frequency divided by 8. For example, if the slave is running at a clock frequency of 8MHz, the JTAG clock at TCK cannot run any faster than 1MHz. |
TDI | Test Data In | Output | Input | This signal carries data that is sent from the master to the slave. |
TDO | Test Data Out | Input | Output | This signal carries data that is sent from the slave back to the master. |
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