多功能波形发生器VHDL程序与仿真

文章摘要： lcd : out std_logic_vector(7 downto 0); --显示输出 shift : out std_logic_vector(3 downto 0); --位码输出 dd, a : out std_logic_vector( 7 downto 0)); --波形、幅度数据输出end mine4;architecture behav of mine4 issubtype word is std_logic_vecto

多功能波形发生器VHDL程序与仿真,标签：fpga是什么,fpga教程,http://www.88dzw.com

      lcd : out std_logic_vector(7 downto 0);                       --显示输出

      shift : out std_logic_vector(3 downto 0);                      --位码输出

      dd, a : out std_logic_vector( 7 downto 0));                    --波形、幅度数据输出

end mine4;

architecture behav of mine4 is

subtype word is std_logic_vector( 7 downto 0 );

type  unit is array(63 downto 0) of word;

signal ram : unit;

signal qqq : integer range 0 to 250000000;

signal qq : integer range 0 to 78125000;

signal tmp : integer range 0 to 9999;

signal coun : integer range 0 to 78125000;

signal coun0 : integer range 0 to 250000000;

signal b : integer range 0 to 78125000;

signal c : integer range 0 to 500000000;

signal z, con : integer range 0 to 63;

signal f : std_logic_vector( 7 downto 0 );

signal amp, amp0, d : std_logic_vector(7 downto 0);

signal bcd0,bcd1,bcd2,bcd3 : integer range 0 to 9;

signal bcd01,bcd11,bcd21,bcd31 : integer range 0 to 9;

signal bcd00,bcd10,bcd20,bcd30 : integer range 0 to 9;

signal y : integer range 0 to 9;

signal addr : integer range 0 to 63;

begin

qq<=781250 when ss="1000" else

      7812500 when ss="0100" else

      78125000 when ss="0010" else

      78125;

--qq信号对应SW=0时的档位选择信号SS，实现方波A和其他三种波形的频率预置

qqq<= 500000 when ss="1000" else 

      5000000 when ss="0100" else

      50000000 when ss="0010" else

50000;

--qqq信号对应SW=1时的档位选择信号SS，实现方波B的频率预置

process(clk)

--此进程分别描述了各种波形的频率、幅度（方波A的占空比）调节以及各种波形的任意线

--形叠加等。

variable count4 : integer range 0 to 6250000;

variable count : integer range 0 to 78125000;

variable count3 : integer range 0 to 250000000;

variable count1 : integer range 0 to 12500000;

variable count0 : integer range 0 to 3249999;

variable ddd : std_logic_vector(9 downto 0);

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