基于FPGA和单片机的串行通信接口设计

文章摘要： if (txcnt_r=7) then state<=odd1;cou<=cou+1; end if; when odd1=> --奇校验位 if ddb='1' then sout1<='0';state<=stop1; else sout1<='1';state<=st

基于FPGA和单片机的串行通信接口设计,标签：eda技术,eda技术实用教程,http://www.88dzw.com
              if (txcnt_r=7) then
                 state<=odd1;cou<=cou+1;
              end if;
         when odd1=>         --奇校验位
              if ddb='1' then
                 sout1<='0';state<=stop1;
              else
                 sout1<='1';state<=stop1;
              end if;
         when stop1=>
              sout1<='1';    --停止位
              if cou<4 then
                 state<=start1;
              else
                 state<=start2;                             
              end if;
         when start2=>
              tsr1:=thr(15 downto 8);
     oddb2:=thr(15 downto 8); 
              sout1<='0';    --起始位  
              txcnt_r<=(others=>'0'); 
              state<=shift2;
         when shift2=>
              oddb<=oddb2(7) xor oddb2(6) xor oddb2(5) xor oddb2(4) xor oddb2(3) xor oddb2(2) xor oddb2(1) xor oddb2(0);
              sout1<=tsr1(0);--数据位
              tsr1(6 downto 0):=tsr1(7 downto 1);
              tsr1(7):='0';
              txcnt_r<=txcnt_r+1; 
              if (txcnt_r=7) then
                 state<=odd2;               

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