基于FPGA和单片机的串行通信接口设计

文章摘要： end if; end if; end process; process(reset,txclk) variable tsr,tsr1,oddb1,oddb2: std_logic_vector(7 downto 0); begin if reset='1' then txcnt_r<=(others=>'0'); sout1<='1'; state<=start

基于FPGA和单片机的串行通信接口设计,标签：eda技术,eda技术实用教程,http://www.88dzw.com
            end if;  
      end if;
  end process;
  process(reset,txclk)
  variable tsr,tsr1,oddb1,oddb2: std_logic_vector(7 downto 0);
   begin
         if reset='1' then
            txcnt_r<=(others=>'0');
                 sout1<='1';
                    state<=start1;                    
                       cou<=0;
         elsif txclk'event and txclk='1' then                 
         case state is
         when start1=>
              if start='1' then            
                 if cou=3 then
                    len<=thr;
                 end if;
                 tsr:=thr(7 downto 0);
     oddb1:=thr(7 downto 0); 
                 sout1<='0'; --起始位 
                 txcnt_r<=(others=>'0');   
                 state<=shift1;
              else
                 state<=start1;
              end if;
         when shift1=>
              oddb<=oddb1(7) xor oddb1(6) xor oddb1(5) xor oddb1(4) xor oddb1(3) xor oddb1(2) xor oddb1(1) xor oddb1(0);
              sout1<=tsr(0); --数据位
              tsr(6 downto 0):=tsr(7 downto 1);
              tsr(7):='0';
              txcnt_r<=txcnt_r+1;

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