简易通用型PCI接口的VHDL-CPLD设计

文章摘要：END IF; END IF; END PROCESS; - - 操作信号的产生 addr < = addr-map WHEN state=s3 OR state=s4 ELSE "ZZZZZZZZZZZZZ" trdy < = '0' WHEN state=s3 OR state=s4 OR state=s5 ELSE '1'; devsel < = '0'WHEN state=s3 OR state=s4 OR state=s5 ELSE'1'; cs < ='0'W

简易通用型PCI接口的VHDL-CPLD设计,标签：fpga是什么,fpga教程,http://www.88dzw.com

END IF;

END IF;

END PROCESS;

- - 操作信号的产生

addr < = addr-map WHEN state=s3 OR state=s4

ELSE "ZZZZZZZZZZZZZ"

trdy < = '0' WHEN state=s3 OR state=s4 OR state=s5

ELSE '1';

devsel < = '0'WHEN state=s3 OR state=s4 OR state=s5

ELSE'1';

cs < ='0'WHEN state=s3 OR state=s4 ELSE '1';

r-w < =NOT clk WHEN write='0'AND (state=s3 OR state=s4)ELSE'1';

state-change:PROCESS(clk,rst) - - 状态机的变化

BEGIN

IF rst='0'THEN state < = s0;

ELSIF falling-edge(clk)THEN

CASE state IS

WHEN s0 = >

IF frame='1'AND irdy='1'THEN state < = s0;

ELSIF frame='0' AND irdy= '1' THEN state < = s1;

END IF;

WHEN s1 = >

IF cs_map='1'OR (read='1'AND write ='1')

THEN state < = s0;

ELSIF irdy='1'AND read='0' THEN state < =s2;

ELSIF frame='0'AND irdy='0'AND write='0'

THEN state < = s3;

ELSIF frame='1'AND irdy='0'AND write='0'

THEN state < = s4;

END IF;

WHEN s2 = >

IF frame='1'AND irdy='1'THEN state < = s0;

ELSIF frame='0'AND irdy='0'AND read='0'

THEN state < = s3;

ELSIF frame='1'AND irdy='0'AND read='0'

THEN state < = s4;

END IF;

WHEN s3 = >

IF frame='1'AND irdy='1'THEN state < = s0;

ELSIF frame='0' AND irdy= '1' THEN state < = s5;

ELSIF frame='1'AND irdy='0' THEN state < =s4;

ELSIF frame='0' AND irdy= '1' THEN state < = s3;

END IF;

WHEN s4 = >

ELSIF frame='1'AND irdy='0'THEN state < = s4;

END IF;

WHEN s5 = >

IF frame='1'AND irdy='1'THEN state < = s0;

ELSIF frame='0' AND irdy= '0'THEN state < = s3;

ELSIF frame='1'AND irdy='0' THEN state < =s4;

ELSE state < = s5;

END IF;

WHEN OTHERS = > state < = s0;

END CASE;

END IF;

END PROCESS state_change;

END behave。

图5

5 MaxPlusII的验证

设计CPLD时，可使用MaxPlusII软件来进行逻辑综合、功能模拟与定时分析。本例选用 Altera 的Max7000系列在系统可编程器件EPM7064SLC84-5。图5所示是其读写访问的仿真波形图。

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