好用的Verilog串口UART程序

文章摘要： rx_empty <= 0; rx_frame_err <= 0; // Check if last rx data was not unloaded, rx_over_run <= (rx_empty) ? 0 : 1; end end end end end endif (!rx_enable) begin rx_busy <= 0;en

好用的Verilog串口UART程序,标签：eda技术,eda技术实用教程,http://www.88dzw.com
                 rx_empty     <= 0;
                 rx_frame_err <= 0;
                 // Check if last rx data was not unloaded,
                 rx_over_run <= (rx_empty) ? 0 : 1;
               end
            end
          end
       end
    end
end
if (!rx_enable) begin
    rx_busy <= 0;
end
end

// UART TX Logic
always @ (posedge txclk or posedge reset)
if (reset) begin
tx_reg        <= 0;
tx_empty      <= 1;
tx_over_run   <= 0;
tx_out        <= 1;
tx_cnt        <= 0;
end else begin
   if (ld_tx_data) begin
      if (!tx_empty) begin
        tx_over_run <= 0;
      end else begin
        tx_reg   <= tx_data;
        tx_empty <= 0;
      end
   end
   if (tx_enable && !tx_empty) begin
     tx_cnt <= tx_cnt + 1;
     if (tx_cnt == 0) begin
       tx_out <= 0;
     end
     if (tx_cnt > 0 && tx_cnt < 9) begin
        tx_out <= tx_reg[tx_cnt -1];
     end
     if (tx_cnt == 9) begin
       tx_out <= 1;
       tx_cnt <= 0;
       tx_empty <= 1;
     end
   end
   if (!tx_enable) begin
     tx_cnt <= 0;
   end
end

endmodule

上一页  [1] [2] [3]